1. Field of the Invention
This invention relates to the field of physical circuit design and, more particularly, to the placement of a design.
2. Description of the Related Art
Designs for Field Programmable Gate Arrays (FPGA's) have become increasingly complex and heterogeneous. Modern FPGA designs can include a variety of different components or resources including, but not limited to, block random access memory (RAM), multipliers, processors, and the like. This increasing complexity makes placement of circuit design components more cumbersome.
Components of circuit designs traditionally have been placed through a series of discrete phases or tasks. Each task is performed sequentially and independently of the others. More particularly, for a given circuit design, a general placement is first performed. The general placement assigns locations on the physical circuit design or chip to inputs and outputs (I/O's).
After the general placement, the I/O assignments are analyzed and relocated as necessary to ensure that the I/O's conform with select I/O standards. The select I/O standards ensure that I/O's located on a same bank of the physical circuit design do not conflict with one another.
The I/O's of a FPGA device can be configured to conform to any one of a variety of different I/O standards. Not all of these standards, however, are compatible with one another. To avoid incompatibility issues, the I/O's of a FPGA circuit design are arranged in groupings called banks. While banks can vary from one circuit design to another, typically, banks span approximately one-half the length of an edge of a chip. Accordingly, a conventional rectangular chip can include 8 banks of I/O's, 2 per side. The I/O's within each bank must conform to I/O standards that are compatible with one another.
After the I/O's are placed, local clock sources can be assigned to physical locations on the circuit design. While the task of placing the local clock sources begins after the placement of the I/O's, the task operates in an independent manner. In other words, the local clock placement task operates without any knowledge of I/O assignments or design constraints determined during the general I/O placement task or the select I/O placement task.
The local clock source placement task seeks to control or minimize clock skew and clock signal delay by assigning local clock sources to particular physical locations within the circuit design. Once the local clock sources are assigned to locations, the loads of the local clock sources of the circuit design can be constrained. The circuit design can be divided into one or more areas often referred to as windows. As such, the loads for each local clock source can be assigned to a particular window as dictated by predetermined design constraints for minimizing clock skew and clock signal delay.
Finally, the global clock sources can be assigned to physical locations on the circuit design. Like the other placement tasks, the global clock placement task begins executing without any knowledge of the placement of I/O's or local clock sources. Once the global clock sources are assigned to locations, the loads of the global clock sources can be assigned to windows of the circuit design.
This placement strategy, however, fails to acknowledge the interdependencies of each respective placement task. That is, while a proper placement may be determined after the I/O's are placed, the subsequent task of placing local clock sources may lead to an improper or illegal circuit placement with respect to design constraints developed for the I/O's during the I/O placement task. In other words, the placement developed by the local clock placement task may disregard requirements determined by the I/O placement task, for example by locating incompatible I/O's within the same bank. Similarly, the global clock placement task may determine location assignments for the global clocks which disregard design constraints determined for the local clocks.
Despite the fact that each placement task influences the other placement tasks, each is performed without incorporating any knowledge of design constraints determined in prior tasks. What is needed is a technique in which design constraints and placement information determined during each individual placement task can be utilized and incorporated in subsequent placement tasks.